1. Field of the Invention
The present invention relates generally to a memory device, and more particularly to a nonvolatile memory device and a method of programming the same.
A claim of priority is made to Korean Patent Application No. 2004-85748 filed on Oct. 26, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memories are an essential part of most modern electronic systems such as computers and other digital logic platforms. Unfortunately, however, the performance of the electronic systems is often limited by the speed and the capacity of the semiconductor memories. In addition, the physical size of memory chips often places a restriction on the amount of miniaturization that can take place in the electronic systems. Because of the limiting effect that semiconductor memories have on modern electronic systems, there is a continuing need to create faster, more highly integrated semiconductor memories. In order to do so, improvements need to be made to the manufacturing technologies used to create these memories. In particular, processing techniques for creating more densely integrated, higher frequency semiconductor memories need to be developed.
Semiconductor memory devices are generally grouped into two broad categories: volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Briefly, volatile semiconductor memory devices provide persistent data storage as long as power is supplied to the devices, but they lose the data once the power is cut off. Nonvolatile semiconductor memory devices, on the other hand, provide persistent data storage even when power to the devices is cut off or suspended.
Because of their ability to provide persistent data storage even when power is cut off, nonvolatile memory devices are commonly used to provide long term storage for data such as program files and microcode. Nonvolatile memory devices are frequently used in application areas such as personal computers, aerospace electronic engineering, communication systems, and consumer electronics.
Some nonvolatile semiconductor memories are adapted for reprogramming and others are not. For example, due to design limitations, mask-programmed read-only memory (MROM) and programmable read-only memory (PROM) can be programmed only once during their lifetime. Erasable programmable read-only memory (EPROM) can be reprogrammed, but only after exposing it to ultraviolet light for several minutes to erase previously stored data. Electrically erasable programmable read-only memory (EEPROM), on the other hand, provides efficient reprogramming capability by allowing memory cells to be reprogrammed by simply applying electric fields to the cells. EEPROMs can generally be reprogrammed more than one hundred thousand times during their lifetime.
Flash memory is a special type of EEPROM in which multiple memory blocks are erased or programmed by a single programming operation. The performance of flash memory is generally superior to that of normal EEPROM, which only allows one memory block to be erased or programmed at a time. In addition, flash memory provides fast access times for read operations and is resistant to physical shock, thus making it an attractive option for high performance portable devices such as cellular phones and personal digital assistants (PDAs).
A typical flash memory comprises an array of transistors called cells, wherein each cell has a source and a drain formed on a substrate and two gate structures formed on the substrate between the source and the drain terminals. The two gate structures generally comprise a floating gate surrounded by an insulating layer and a control gate formed on the floating gate. The floating gate is used to store electrons determining a logic state for the cell.
A flash memory cell is read by placing a voltage on its control gate and detecting whether a current flows between its drain and source. Depending on how many electrons are stored in the floating gate, the voltage applied to the control gate will either allow current to flow between the drain and the source or it will not. For example, where a large number of electrons is stored in the floating gate, the electrons have a canceling effect on the voltage applied to the control gate, thereby affecting whether current flows between the drain and the source. In other words, the electrons stored in the floating gate modify the threshold voltage of the cell, i.e. the voltage that has to be applied to the control gate in order for current to flow between the drain and the source.
Due to variations in flash memory cells such as their geometry or a voltage used to program the memory cells, there tends to be variation in the threshold voltages of flash memory cells that have been programmed. Where the variation in the threshold voltages of the memory cells is not properly regulated, it can cause the flash memory to have poor performance.
In order to regulate a threshold voltage distribution for programmed memory cells, the memory cells are generally programmed using an incremental step pulse programming (ISPP) scheme such as that illustrated by FIG. 1. Referring to FIG. 1, a programming voltage VWL is applied to a wordline. Programming voltage VWL is increased in multiple programming loop iterations executed during a programming operation. Each programming loop comprises a programming period and a program verifying period. In each programming loop, programming voltage VWL is incremented by an amount ΔV. During the programming operation, a threshold voltage Vt of a cell being programmed increases by amount ΔV in each programming loop. In order to minimize variation in the threshold voltage distribution, amount ΔV should be small. As increment ΔV becomes smaller, the number of programming loops becomes larger. Since there is a tradeoff between the number of programming loops required and the variance of the threshold voltage distribution, ΔV should be chosen to minimize the variance of the threshold voltage as much as possible without significantly limiting the performance of the memory device by requiring too many programming loops.
A programming scheme for a nonvolatile memory device is disclosed, for example, in U.S. Pat. No. 6,266,270. Circuits for generating programming voltages are disclosed, for example, in U.S. Pat. No. 5,642,309 and in Korean Patent Publication No. 2002-39744.
In programming a NOR flash memory device using the ISPP scheme, a wordline voltage of 10V is applied to the control gate of a flash memory cell, a bitline voltage of 5˜6V is applied to the drain of the flash memory cell, and a voltage less than 0V (e.g., −1V) is applied to the bulk (or substrate) of the flash memory cell. In general, a current Icell flowing through the flash memory cell is (VGS−Vt)2, where Vt is proportional to a threshold voltage of the flash memory cell and VGS is a gate-to-source voltage of the flash memory cell.
The bitline voltage is typically generated and maintained by a charge pump. Where the value of current Icell is larger than the capacity of the charge pump generating the bitline voltage, the bitline voltage is reduced. Where the bitline voltage is reduced beyond a certain amount, the threshold voltage of the flash memory cell fails to increase to a desired level during a programming operation, as indicated by a broken line in FIG. 1. Under these conditions, the difference between the wordline voltage and the threshold voltage becomes progressively larger as more programming loop iterations are executed using the ISPP scheme. As a result, the quality of programming gradually degrades to the point where programming failures occur.
What is needed, therefore, is a way to prevent programming failures from occurring due to a drop in the bitline voltage.